1. Field of the Invention
The present invention relates to semiconductor device manufacturing, and more specifically, to modeling and simulation of circuit performance degradation.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, as well as in the manufacture of integrated circuit devices incorporating such devices.
There is a trend toward high device densities within integrated circuit devices. To achieve these high device densities, small features on semiconductor wafers are required. To achieve these higher densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers. These may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and spacing and length of a MOS (metal oxide semiconductor) gate trace, which may have varying intra-chip lengths depending upon their position relative to the devices to which they are connected.
Progress in these manufacturing technologies comes at the cost of increased complexities in semiconductor processes, especially at sub-micron levels, which have attendant issues not previously addressed by prior design models and simulation methods. For example, systematic intra-chip spatial variability is a significant issue for chip designers, driving the need for more effective interaction between design models, simulation methods, and manufacturing techniques.
In complementary metal oxide semiconductor (CMOS) technologies, an important processing parameter affecting circuit performance is the gate length (Lgate) of a transistor. Spatial variations in Lgate affect circuit timing properties, which can lead to timing errors and performance loss.
Furthermore, significant and systematic, as opposed to minor and random, spatial intra-chip variability of transistor gate lengths, can lead to relatively large variations in circuit path delays. These large variations can result in circuit failure if variability is not properly addressed at the design stage. For example, the delay of the critical path of a combinational logic block can vary by as much as 17%, with global clock skew increasing by as much as 8%.
Thus intra-chip transistor Lgate variation can have a substantial and detrimental effect on overall circuit performance, resulting in races or hold time failures. Moreover, analysis indicates that spatial, rather than proximity-dependent, systematic transistor Lgate variability can be a major cause of circuit failure.
An estimation of such circuit failure could be calculated for given circuit and process parameters, based on individual device characteristics and the related effect of spatial dependence on their respective location within the chip. Furthermore, this detrimental effect of intra-chip transistor Lgate variability could be substantially mitigated in the semiconductor design phase, by accurately predicting the improvement of their respective operating characteristics by modeling changes in device location.
However, no such method currently exists for accurate modeling and simulation of the effect of intra-chip transistor Lgate spatial variability on circuit failure.